19FEBRUARY 2024Since only one failed sample is usually brought into the laboratory, failure such as `accidentally cut off the faulty part' is not acceptable. ITES has the optimum equipment for these three processes and the unique precision processing technology for failed specimens to maximize equipment performance, resulting in an extremely high failure identification rate. This is the reason why they have many repeat customers.Yasuyuki Igarashi, President and CEO of ITES, emphasizes the value of its precise diagnostics. "With the insights we provide, manufacturers can make quick, specific enhancements to their production line, significantly reducing the time needed to improve the manufacturing process."Rightly so, in a recent case, ITES pinpointed a minor leakage in a semiconductor device, that seemed to be caused by a foreign material introduced during the formation of the transistor gate, and succeeded in identifying a manufacturing process that needs to be improved. The critical insights enabled the manufacturer to refine their processes and prevent future occurrences of this issue, consequently reducing manufacturing costs.ITES's Advanced EVC Method for Capturing Critical Latent Defects in SiC ReliabilityITES's EVC--Expansion, Visualization, and Contraction--method is a groundbreaking process set to transform semiconductor defect detection and device longevity. This technique replaces the laborious burn-in process traditionally used by device manufacturers, which involves overcurrent stress-testing each individual chip. It is both time-intensive and less efficient, which raises the total cost of production.In contrast, EVC's innovative process begins with the application of an ultraviolet (UV) laser system to illuminate the entire wafer. It is designed to reveal SiC-specific latent defects that would otherwise remain hidden, and cannot be detected by existing inspection systems. Once these defects expand, they become detectable at the wafer level by ITES's photoluminescence method. This early detection is crucial. It allows device manufacturers to map out and address potential defects before circuit fabrication. With such defect mapping, manufacturers can avoid incorporating flawed areas into their designs, preemptively eliminating future reliability issues.Another key process is the heating of the wafers to temperatures around 600 to 800 degrees Celsius for about an hour. The thermal treatment causes the expanded defects to contract and return to their original state. In the current burn-in With the insights we provide, manufacturers can make quick, specific enhancements to their production line, significantly reducing the time needed to improve the manufacturing process
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