J -Wing Teh
J-Wing Teh is currently serving as the director of silicon and systems design engineering at AMD. With a strong background in the semiconductor industry, he brings a wealth of knowledge and experience to his role. His responsibilities involve overseeing various aspects of silicon design and system engineering, contributing to the innovative solutions that AMD is known for. His leadership role at AMD is instrumental in driving the company’s mission forward in the tech industry.
Could you provide a brief overview of your experience in the industry, specifically your role as the director of silicon and systems at AMD?
I started my career in the semiconductor industry right after completing my master’s degree. My first role was at Intel Microelectronics, where I worked on chipset design, specifically focusing on the verification of audio controllers.
Over the years, I held various roles in physical design, front-end design coding, and System on Chip (SoC) integration and verification. I also had the opportunity to spend a year in the US, working on the next-generation USB controller. In 2009, I was a part of a centralized IP provider team that focused on developing methodologies and infrastructure for USB and other controllers.
After approximately eight years at Intel, I moved to a company called Altera that makes reconfigurable chips. Here, I worked on IPs and subsequently revisited methodology and infrastructure, applying the knowledge I gained from Intel to enhance the development methodology for reconfigurable hardware.
During the data center boom around 2017, I led data center IP teams, working on protocols typically used in data centers like PCI Express, CXL, UPI, etc.
In 2022, I finally took on a new role as Director of Silicon and Systems at AMD. Here I was tasked with the challenge of setting up a new site in Penang, Malaysia. I took it as an opportunity and built a team of around 50 people in about a year and three months.
What are some of the trends that are shaping the silicon wafer market currently?
Currently, the silicon wafer market is being significantly influenced by AI. This trend was sparked by the introduction of OpenAI's GPT, which amazed people with its ability to answer any typed question. However, to run such capabilities, powerful hardware or processing engines are required, a domain where Nvidia and AMD are the current leaders.
“Success lies not just in pushing boundaries, but also in finding creative solutions to the challenges that arise. By embracing continuous learning and innovation, we can navigate the complexities of the market and bring about positive change.”
Despite concerns about AI replacing jobs, I views AI as a tool for efficiency, much like how Microsoft Excel enhanced data processing. I foresee AI assisting in silicon or chip design tasks, improving efficiency while still necessitating human interaction. The influence of AI is anticipated to grow over the next three to five years before gradually tapering down.
What are the challenges that the silicon wafer industry is facing today?
The semiconductor industry is currently facing two primary challenges. The first is a human resources issue. The industry’s growth has led to a significant increase in the demand for chip development. However, the current workforce is insufficient to meet these demands even with the aid of automation. This is especially due to the dwindling number of graduates in science, technology, and engineering fields.
The second challenge is technological. As per Moore’s Law, the number of transistors on a silicon chip is expected to double approximately every 18 months. However, it becomes difficult to maintain this trend as the industry advances towards smaller processors of around 2-3 nanometers.
One approach has been to stack multiple silicon layers, but this has led to larger chip sizes. The industry now faces the challenge of whether it can go beyond one nanometer, which might necessitate finding a different material or a new manufacturing method.
Are there any recent advancement that has improved silicon wafer manufacturing efficiency and yield?
Yield can be identified as a persistent challenge as it often takes two to three years to develop the optimal manufacturing process for a new type of chip. Intel’s 10 nanometer processor for example, took years to become profitable due to initial low yields.
The industry responds to these issues by being innovative. One approach is to slow down the scaling of the manufacturing process. Instead of continually trying to make smaller chips, manufacturers are exploring ways to stack silicon layers together. This allows them to increase the number of transistors without reducing the size of the silicon.
The advancements have led to discussions about advanced packaging and wafer technologies. These include techniques for dye and 3D dye, which aim to increase the number of transistors on the silicon while maintaining yield. The industry is now able to mix and match different processors of silicon, combining silicon of different sizes (like 10 nanometer and 5 nanometer) together. This approach allows them to meet their needs without having to continually reduce the size of the silicon.
What would be your piece of advice to the upcoming industry leaders or professionals in the industry?
As someone who has navigated the industry, I would advise newcomers and emerging leaders to embrace continuous learning. What we learn in universities is only a small fraction of what is needed for a successful career. It's important to not be afraid of making mistakes and getting hands-on experience and learning from failures for professional growth. Playing it too safe can limit learning and progress. Instead, I would advise individuals to take risks, make mistakes, recover, and learn from these experiences.
